********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 05, 2014
*ECN S14-0989, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR640ADP D G S 
M1 3 GX S S NMOS W= 19280000u L= 0.25u 
M2 S GX S D PMOS W= 19280000u L= 0.06u
R1 D 3 1.37e-03 3.039e-03 6.861e-06 
CGS GX S 1.522e-09 
CGD GX D 3.688e-11 
RG G GY 1.2 
RTCV 100 S 1e6 3.112e-04 -1.843e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 19280000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 5.975e-06 NSUB = 6.32e+16 
+ KAPPA = 1.000e-06 NFS = 7.866e+10 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 9.340e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.910e-08 TREF = 25 BV = 41 
+RS = 2.423e-02 N = 1.072e+00 IS = 3.065e-12 
+EG = 8.184e-01 XTI = 9.999e+00 TRS = 1.000e-05 
+CJO = 4.383e-10 VJ = 1.338e+00 M = 2.774e-01 ) 
.ENDS 
